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Chapter 13: Problem 11

For a dual-slope converter, describe what occurs during the fixed time interval and the count interval.

Short Answer

Expert verified
During the fixed time interval of a dual-slope converter, the input signal is integrated for a fixed duration. During the count interval, the previous signal is discharged at the same rate and a counter measures how long this takes, this count represents the original analog signal in digital form.

Step by step solution

01

Explanation of the Fixed Time Interval

In the fixed time interval of a dual-slope converter, the input signal is integrated for a fixed period. This is usually accomplished by connecting a fixed reference voltage to the integrator for a predetermined duration. During this time, the level of the input signal is continuously summed.
02

Explanation of the Count Interval

Following the fixed time interval, the count interval begins. In this stage, the reference voltage is reversed to de-integrate or discharge the integrated signal. A counter then begins to count the number of clock pulses that pass in this time until the output of integrator reaches zero volts. At this point, the count stops.
03

Conclusion and Understanding of the Process

These two intervals, taken together, make up the operation of the dual-slope converter. The fixed time interval measures the input signal by integrating it over time. The count interval is then used to generate a digital signal that accurately represents the original analog signal. The count during count interval corresponds to the magnitude of the analog input signal.

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Most popular questions from this chapter

Draw the diagram of a 741 op-amp operated from \(\pm 15-\mathrm{V}\) supplies with \(V_{i}(-)=0 \mathrm{~V}\) and \(V_{i}(t)=+5 \mathrm{~V}\). Include terminal pin connections.

Sketch the input and output waveforms for a one-shot using a 555 timer triggered by a \(10-\mathrm{kHz}\) clock for \(R_{A}=5.1 \mathrm{k} \Omega\) and \(C=5 \mathrm{nF}\).

What is the maximum count interval using a 12 -stage counter operated at a clock rate of \(20 \mathrm{MHz}\) ?

Describe the signal conditions for current-loop and RS-232C interfaces.

What voltage resolution is possible using a 12 -stage ladder network with a \(10-\mathrm{V}\) reference voltage?
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